1. Field of the Invention
This invention relates generally to the manufacture of high performance integrated circuits on semiconductor devices. More specifically, this invention relates to optimizing the manufacture of high performance integrated circuits on semiconductor devices using simulated wafer electrical test data (WET) from current and previous layer data. Even more specifically, this invention relates to accurate disposition of wafer lots in the manufacture of semiconductor device based on remaining available specification margins in future processes and current processing results.
2. Discussion of the Related Art
In the typical semiconductor manufacturing facility, many simulation and analysis tools have been implemented to assist the process integration and device development efforts. These simulation and analysis tools, however, are typically employed to provide an indication of general trends. The latent potential of reducing the number of silicon runs and speeding up the process optimization cycle has not been fully achieved. One of the primary reasons the process optimization cycle has not been achieved is that the accuracy of the data obtained cannot be established to the degree necessary to determine the dependability of the simulation systems. The accuracy of the data obtained can only be achieved by a complete and detailed engineering calibration of the simulation system. This calibration, however, demands extensive engineering resources and data from multiple silicon production runs which, in turn, is usually only available at the latter stages of the process development or early production cycles.
In addition, process optimization for a technology that has completed qualification and is ramping-up production could receive great benefit from the extensive embedded device physics contained in advanced complex simulation tools.
Current trends in semiconductor process development include the use of these simulation tools to predict certain wafer electrical tests (WET) device performance characteristics based on a predetermined set of process values. The use of these simulation tools has been very effective. Additionally, optimal performance of current large-scale integrated devices can be predicted by a subset of critical WET performance parameters. These performance criteria include speed, operating temperature, power utilization, and reliability.
Furthermore, current manufacturing technology utilizes in-line statistical evaluation of critical parametric values at most module steps in the overall process flow. These statistical values are used to maintain control of the process, at the particular process module in question, often without regard to previous processing results. Often the goal of manufacturing is to meet not only yield goals, but certain performance goals as well. Currently, to do this it is necessary to force certain values to meet very strict specifications, such as shifting polysilicon gate critical dimensions (CD) or increasing or increasing threshold adjust implant, and hope that other process module variations will not adversely affect performance.
Further trends in semiconductor processing are continually moving towards more automated or system level control of individual equipment components to maintain a high degree or confidence in the overall process environment. The standard practice has been to require strict adherence to a rigidly controlled specification limit for certain process parameters such that natural variation within those specifications at various critical steps would not permit device performance to vary outside of the desired operating range. The current practice is to continually adjust toward the middle of the specification, making recipe modifications as necessary to implement the fine-tuning, and these adjustments are based on the current trend of the equipment. These specifications stand alone at the individual process steps and are generally not affected by the previous processing results of the lot.
A process simulation tool has been disclosed in the Application Serial No. 08/985,566, issued as U.S. Pat. No. 5,866,437, entitled DYNAMIC PROCESS WINDOW CONTROL USING SIMULATED WET DATA FROM CURRENT AND PREVIOUS LAYER DATA that uses a method to achieve optimum performance by providing a process control window or specification for the current module by utilizing the previous process step statistical data as a baseline that is entered into the process simulation tool. Such a process control window has the potential of being much wider than current specifications due to the previous layer parameters and their effects being precisely known and can be considered dynamic since the process control window can change based on actual previous layer data. The simulation tool would be preset to optimize the process to hit certain critical WET parametrics. Using the previous data baseline, and the WET goals, the simulator tool would then provide direction by providing a process control window for the remaining operations to achieve those goals.
A method of automatically making adjustments to the process recipes for the remaining operations has been disclosed in the Application, Serial No. 08/985,470, issued as U.S. Pat. No. 6,041,270, entitled AUTOMATIC RECIPE ADJUST AND DOWNLOAD BASED ON PROCESS CONTROL WINDOW that uses a simulation tool to determine a set of predicted wafer electrical test measurements that are compared to a set of target wafer electrical test measurements to obtain a set of optimized process parameters for the equipment for the next process. The optimized process parameters are compared to the equipment characteristics for the equipment of the next process and the process parameters for the next process are automatically adjusted.
The above improvements to the manufacturing process provide methods of adjusting a current or future process to compensate for a previous process that was not within the pre-established specifications. However, with some processes that may be out of specification and other processes that have been adjusted to compensate for the processes that are out of specification, there is currently no way for a process engineer to make disposition recommendations based on out-of-specification values at a current operation or module, while taking into account the effects of previous steps and the effect the current values will have on later steps or device performance.
Therefore, what is needed is a method to predict expected device performance based on remaining available specification margins at future processes or modules and current processing results.